1. Field of the Invention
The present invention relates to semiconductor devices employing floating gates and isolation trenches.
2. Related Art
As is well known, semiconductor devices may be implemented with various structures to provide non-volatile memories which are useful in a variety of different applications. Stacked gate structures that include stacked floating gates and control gates are often used to fabricate non-volatile memory cells (e.g., flash memory cells) which may be selectively programmed, unprogrammed, and reprogrammed through the application of appropriate voltages.
Large numbers of non-volatile memory cells may be fabricated on a common substrate to provide an array of non-volatile memory cells. In order to isolate individual non-volatile memory cells from each other, various isolation techniques have been developed. Shallow trench isolation (STI) is one such technique. In this approach, a plurality of trenches are formed between active areas of the non-volatile memory cells. The trenches are filled with a dielectric which serves to isolate active areas (for example, source/drain implants and active channels) of adjacent non-volatile memory cells.
It is important that the trenches are sufficiently filled with the dielectric in order to provide meaningful isolation between active areas. Unfortunately, conventional manufacturing techniques used in the formation of stacked gate structures can often damage the dielectric in the trenches, thereby compromising the isolation provided by the trenches.
For example, conventional non-volatile memory cells may include a gate dielectric layer formed on top of the trenches and active areas, and a polysilicon layer formed on top of the gate dielectric layer. In order to form control gates for the non-volatile memory cells, the control gate topography is masked and the unmasked portions of the polysilicon layer and the underlying gate dielectric layer are etched in a single etching step.
During the etching, the entirety of the polysilicon layer and the gate dielectric layer above the trenches are removed. Unfortunately, because of the lack of selectivity between these two exposed layers during etching, the underlying trenches between the floating gates may also be significantly etched and damaged. In particular, the etching may cause significant amounts of the dielectric in the trenches between the active areas to be etched away.
As a result, the isolation characteristics of the trenches can become seriously compromised. Source/drain implants provided in the active areas may not be sufficiently isolated from each other, resulting in short circuit between active areas of adjacent non-volatile memory cells. Such conditions can cause complete failure of one or more non-volatile memory cells. Although deeper isolation trenches may sometimes be employed to reduce such effects, the use of deeper trenches can significantly increase the self-aligned source (SAS) resistance and furthermore may be impractical for semiconductor devices having small feature sizes (for example, filling the trenches with the dielectric may be impractical).
Accordingly, there is a need for an improved manufacturing process for non-volatile memory cells. In particular, for example, there is a need for a manufacturing process that reduces the loss of dielectric material in trenches while still providing sufficient etching to delineate stacked gate structures of the non-volatile memory cells.